"A Highly Parallel Hardware Architecture of Table-Based CABAC Bit Rate ..."

Yuanzhi Zhang, Chao Lu (2019)

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DOI: 10.1109/TCSVT.2018.2830126

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type: Journal Article

metadata version: 2025-01-19

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Yuanzhi Zhang, Chao Lu:
A Highly Parallel Hardware Architecture of Table-Based CABAC Bit Rate Estimator in an HEVC Intra Encoder. IEEE Trans. Circuits Syst. Video Technol. 29(5): 1544-1558 (2019)

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