Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A novel frame reordering scheme and a high speed VLSI architecture of ..."

Kyeong-Yuk Min, Jong-Wha Chong (2009)

> Home

Details and statistics

DOI: 10.1109/TCE.2009.5373815

access: closed

type: Journal Article

metadata version: 2020-07-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tce/MinC09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tce/MinC09
Kyeong-Yuk Min, Jong-Wha Chong:
A novel frame reordering scheme and a high speed VLSI architecture of multiple reference frame motion estimator for H.264/AVC. IEEE Trans. Consumer Electron. 55(4): 2394-2400 (2009)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.