"A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme ..."

Yudeng Lin et al. (2023)

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DOI: 10.1109/TCSII.2022.3224470

access: open

type: Journal Article

metadata version: 2023-07-27

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Yudeng Lin, Jianshi Tang, Bin Gao, Qi Qin, Qingtian Zhang, He Qian, Huaqiang Wu:
A High-Speed and High-Efficiency Diverse Error Margin Write-Verify Scheme for an RRAM-Based Neuromorphic Hardware Accelerator. IEEE Trans. Circuits Syst. II Express Briefs 70(4): 1366-1370 (2023)

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