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"A 2.5-5.0-GHz Clock Multiplier With 3.2-4.5-mUIrms Jitter and ..."

Jaya Deepthi Bandarupalli, Saurabh Saxena (2022)

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DOI: 10.1109/TCSII.2022.3177885

access: closed

type: Journal Article

metadata version: 2022-09-22

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Jaya Deepthi Bandarupalli, Saurabh Saxena:
A 2.5-5.0-GHz Clock Multiplier With 3.2-4.5-mUI_rms Jitter and 0.98-1.06 mW/GHz in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3714-3718 (2022)

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