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"A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate ..."

Xiaoteng Zhao et al. (2021)

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DOI: 10.1109/TCSI.2020.3038865

access: closed

type: Journal Article

metadata version: 2021-01-26

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  dblp key:
  - journals/tcasI/ZhaoCMM21
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  - https://dblp.org/rec/journals/tcasI/ZhaoCMM21
Xiaoteng Zhao, Yong Chen, Pui-In Mak, Rui Paulo Martins:
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 89-102 (2021)

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