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"Validation of a Full-Chip Simulation Model for Supply Noise and Delay ..."

Yasuhiro Ogasahara et al. (2007)

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DOI: 10.1109/TCSII.2007.901574

access: closed

type: Journal Article

metadata version: 2024-06-17

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  - https://dblp.org/rec/journals/tcas/OgasaharaEHSO07
Yasuhiro Ogasahara, Takashi Enami, Masanori Hashimoto, Takashi Sato, Takao Onoye:
Validation of a Full-Chip Simulation Model for Supply Noise and Delay Dependence on Average Voltage Drop With On-Chip Delay Measurement. IEEE Trans. Circuits Syst. II Express Briefs 54-II(10): 868-872 (2007)

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