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"A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth."

Arashk Norouzpour-Shirazi et al. (2008)

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DOI: 10.1109/TCSII.2008.926792

access: closed

type: Journal Article

metadata version: 2020-05-27

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  - journals/tcas/Norouzpour-ShiraziMAS08
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  persistent URL:
  - https://dblp.org/rec/journals/tcas/Norouzpour-ShiraziMAS08
Arashk Norouzpour-Shirazi, S. Arash Mirhaj, Shahin Jafarabadi-Ashtiani, Omid Shoaei:
A Novel Low Power 1 GS/s S&H Architecture With Improved Analog Bandwidth. IEEE Trans. Circuits Syst. II Express Briefs 55-II(10): 971-975 (2008)

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