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"A Low Power Logic-Compatible Multi-Bit Memory Bit Cell Architecture With ..."

John Lynch, Pedro P. Irazoqui (2014)

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DOI: 10.1109/TCSI.2014.2334791

access: closed

type: Journal Article

metadata version: 2020-05-22

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John Lynch, Pedro P. Irazoqui:
A Low Power Logic-Compatible Multi-Bit Memory Bit Cell Architecture With Differential Pair and Current Stop Constructs. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(12): 3367-3375 (2014)

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