default search action
"Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation."
Mehedi Hasan et al. (2020)
- Mehedi Hasan, Md. Jobayer Hossein, Mainul Hossain, Hasan U. Zaman, Sharnali Islam:
Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1464-1468 (2020)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.