"Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation."

Mehedi Hasan et al. (2020)

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DOI: 10.1109/TCSII.2019.2940558

access: closed

type: Journal Article

metadata version: 2020-10-08

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  - https://dblp.org/rec/journals/tcas/HasanHHZI20
Mehedi Hasan, Md. Jobayer Hossein, Mainul Hossain, Hasan U. Zaman, Sharnali Islam:
Design of a Scalable Low-Power 1-Bit Hybrid Full Adder for Fast Computation. IEEE Trans. Circuits Syst. II Express Briefs 67-II(8): 1464-1468 (2020)

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