"Hardware Efficient Low-Latency Architecture for High Throughput Rate ..."

Chao Cheng, Keshab K. Parhi (2008)

> Home

Details and statistics

DOI: 10.1109/TCSII.2008.2008061

access: closed

type: Journal Article

metadata version: 2024-05-07

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/ChengP08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/ChengP08
Chao Cheng, Keshab K. Parhi:
Hardware Efficient Low-Latency Architecture for High Throughput Rate Viterbi Decoders. IEEE Trans. Circuits Syst. II Express Briefs 55-II(12): 1254-1258 (2008)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.