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"A novel scheme to reduce test application time in circuits with full scan."

Dhiraj K. Pradhan, Jayashree Saxena (1995)

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DOI: 10.1109/43.476587

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - journals/tcad/PradhanS95
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  - https://dblp.org/rec/journals/tcad/PradhanS95
Dhiraj K. Pradhan, Jayashree Saxena:
A novel scheme to reduce test application time in circuits with full scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1577-1586 (1995)

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