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"A Switch-Level Timing Verifier for Digital MOS VLSI."

John K. Ousterhout (1985)

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DOI: 10.1109/TCAD.1985.1270130

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - https://dblp.org/rec/journals/tcad/Ousterhout85
John K. Ousterhout:
A Switch-Level Timing Verifier for Digital MOS VLSI. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(3): 336-349 (1985)

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