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"PROOFS: a fast, memory-efficient sequential circuit fault simulator."

Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel (1992)

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DOI: 10.1109/43.124398

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - https://dblp.org/rec/journals/tcad/NiermannCP92
Thomas M. Niermann, Wu-Tung Cheng, Janak H. Patel:
PROOFS: a fast, memory-efficient sequential circuit fault simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(2): 198-207 (1992)

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