"A joint gate sizing and buffer insertion method for optimizing delay and ..."

Kerry S. Lowe, P. Glenn Gulak (1998)

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DOI: 10.1109/43.703932

access: closed

type: Journal Article

metadata version: 2020-09-24

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Kerry S. Lowe, P. Glenn Gulak:
A joint gate sizing and buffer insertion method for optimizing delay and power in CMOS and BiCMOS combinational logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(5): 419-434 (1998)

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