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"Post-Silicon Gate-Level Error Localization With Effective and Combined ..."

Binod Kumar et al. (2020)

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DOI: 10.1109/TCAD.2018.2883899

access: closed

type: Journal Article

metadata version: 2020-09-24

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Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh:
Post-Silicon Gate-Level Error Localization With Effective and Combined Trace Signal Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(1): 248-261 (2020)

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