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"Latency-Guided On-Chip Bus-Network Design."
Milenko Drinic et al. (2006)
- Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak:
Latency-Guided On-Chip Bus-Network Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2663-2673 (2006)
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