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"Combining technology mapping and placement for delay-minimization in FPGA ..."

Chau-Shen Chen et al. (1995)

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DOI: 10.1109/43.406709

access: closed

type: Journal Article

metadata version: 2020-09-24

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Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1076-1084 (1995)

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