"Efficient BIST TPG design and test set compaction via input reduction."

Chih-Ang Chen, Sandeep K. Gupta (1998)

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DOI: 10.1109/43.712101

access: closed

type: Journal Article

metadata version: 2020-09-24

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Chih-Ang Chen, Sandeep K. Gupta:
Efficient BIST TPG design and test set compaction via input reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(8): 692-705 (1998)

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