"Test set compaction for combinational circuits."

Jau-Shien Chang, Chen-Shang Lin (1995)

> Home

Details and statistics

DOI: 10.1109/43.469663

access: closed

type: Journal Article

metadata version: 2020-09-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/ChangL95
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/ChangL95
Jau-Shien Chang, Chen-Shang Lin:
Test set compaction for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1370-1378 (1995)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.