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ORCID"Clock skew reduction in ASIC logic design: a methodology for clock tree ..."
Alessandro Balboni et al. (1998)
- Alessandro Balboni, Claudio Costi, Massimo Pellencin, Andrea Quadrini, Donatella Sciuto:
Clock skew reduction in ASIC logic design: a methodology for clock tree management. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4): 344-356 (1998)
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