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"Logic design verification via test generation."
Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland (1988)
- Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland:
Logic design verification via test generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(1): 138-148 (1988)
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