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"Design of Testable VLSI Circuits with Minumum Area Overhead."

Prasad R. Chalasani et al. (1989)

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DOI: 10.1109/12.35841

access: closed

type: Journal Article

metadata version: 2023-04-28

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  dblp key:
  - journals/tc/ChalasaniBAP89
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  persistent URL:
  - https://dblp.org/rec/journals/tc/ChalasaniBAP89
Prasad R. Chalasani, Sudipta Bhawmik, Anurag Acharya, Parimal Palchaudhuri:
Design of Testable VLSI Circuits with Minumum Area Overhead. IEEE Trans. Computers 38(10): 1460-1462 (1989)

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