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"VLSI implementation issues for the 2-D Fermat number transform."

M. Benaissa, Satnam Singh Dlay, A. G. J. Holt (1991)

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DOI: 10.1016/0165-1684(91)90004-3

access: closed

type: Journal Article

metadata version: 2020-02-22

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  - journals/sigpro/BenaissaDH91
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  - https://dblp.org/rec/journals/sigpro/BenaissaDH91
M. Benaissa, Satnam Singh Dlay, A. G. J. Holt:
VLSI implementation issues for the 2-D Fermat number transform. Signal Process. 23(3): 257-272 (1991)

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