"Fault tolerant bus architecture for deep submicron based processors."

N. Venkateswaran, S. Balaji, V. Sridhar (2005)

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DOI: 10.1145/1055626.1055647

access: closed

type: Journal Article

metadata version: 2021-09-16

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N. Venkateswaran, S. Balaji, V. Sridhar:
Fault tolerant bus architecture for deep submicron based processors. SIGARCH Comput. Archit. News 33(1): 148-155 (2005)

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