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ORCID"Low Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA."
Dan Yang et al. (2023)
- Dan Yang
, Xuhan Xu, Tianyang Chen, Yanhao Chen, Junjie Zhang:
Low Latency TOE with Double-Queue Structure for 10Gbps Ethernet on FPGA. Sensors 23(10): 4690 (2023)
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last updated on 2023-09-30 10:26 CEST by the dblp team
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