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"A VLSI design of clock gated technique based ADC lock-in amplifier."

M. Saritha et al. (2022)

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DOI: 10.1007/S13198-022-01747-6

access: closed

type: Journal Article

metadata version: 2024-03-25

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  - journals/saem/SarithaLARASSSV22
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  - https://dblp.org/rec/journals/saem/SarithaLARASSSV22
M. Saritha, M. Lavanya, G. Ajitha, Mulinti Narendra Reddy, P. Annapurna, Menda Sreevani, S. Swathi, S. Sushma, Vallabhuni Vijay:
A VLSI design of clock gated technique based ADC lock-in amplifier. Int. J. Syst. Assur. Eng. Manag. 13(5): 2743-2750 (2022)

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