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"VLSI Architectures for High-Speed Range Estimation."

Raghu Sastry, N. Ranganathan, Ramesh C. Jain (1995)

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DOI: 10.1109/34.406655

access: closed

type: Journal Article

metadata version: 2019-10-26

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  dblp key:
  - journals/pami/SastryRJ95
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  persistent URL:
  - https://dblp.org/rec/journals/pami/SastryRJ95
Raghu Sastry, N. Ranganathan, Ramesh C. Jain:
VLSI Architectures for High-Speed Range Estimation. IEEE Trans. Pattern Anal. Mach. Intell. 17(9): 894-899 (1995)

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