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ORCID"Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias ..."
Atsuki Kobayashi, Kiichi Niitsu (2020)
- Atsuki Kobayashi
, Kiichi Niitsu:
Low-Voltage Gate-Leakage-Based Timer Using an Amplifier-Less Replica-Bias Switching Technique in 55-nm DDC CMOS. IEEE Open J. Circuits Syst. 1: 107-114 (2020)
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