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"Sub-100 nm CMOS circuit performance with high-K gate dielectrics."

Nihar R. Mohapatra et al. (2001)

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DOI: 10.1016/S0026-2714(01)00068-3

access: closed

type: Journal Article

metadata version: 2021-10-08

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  - https://dblp.org/rec/journals/mr/MohapatraDSDR01
Nihar R. Mohapatra, Arijit Dutta, G. Sridhar, Madhav P. Desai, V. Ramgopal Rao:
Sub-100 nm CMOS circuit performance with high-K gate dielectrics. Microelectron. Reliab. 41(7): 1045-1048 (2001)

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