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"Characterization and optimization of junctionless gate-all-around ..."
V. Bharath Sreenivasulu, Vadthiya Narendar (2021)
- V. Bharath Sreenivasulu
, Vadthiya Narendar:
Characterization and optimization of junctionless gate-all-around vertically stacked nanowire FETs for sub-5 nm technology nodes. Microelectron. J. 116: 105214 (2021)
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