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"A method to assess the robustness of cryptographic circuits at the design ..."

M. Arévalo-Garbayo et al. (2014)

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DOI: 10.1016/J.MEJO.2013.12.012

access: closed

type: Journal Article

metadata version: 2022-04-09

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  - https://dblp.org/rec/journals/mj/Arevalo-GarbayoPGLE14
M. Arévalo-Garbayo, Marta Portela-García, Mario García-Valderas, Celia López-Ongil, Luis Entrena:
A method to assess the robustness of cryptographic circuits at the design stage. Microelectron. J. 45(10): 1354-1360 (2014)

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