"An analog systolic neural processing architecture."

Juan Manuel Moreno et al. (1994)

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DOI: 10.1109/40.285224

access: closed

type: Journal Article

metadata version: 2022-06-23

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  - https://dblp.org/rec/journals/micro/MorenoCCMN94
Juan Manuel Moreno, Francisco Castillo, Joan Cabestany, Jordi Madrenas, Andrzej Napieralski:
An analog systolic neural processing architecture. IEEE Micro 14(3): 51-59 (1994)

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