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"A floating-point VLSI chip for the TRON architecture: an architecture for ..."

Shumpei Kawasaki, Mitsuru Watabe, Shigeki Morinaga (1989)

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DOI: 10.1109/40.31476

access: closed

type: Journal Article

metadata version: 2017-05-20

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  dblp key:
  - journals/micro/KawasakiWM89
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  persistent URL:
  - https://dblp.org/rec/journals/micro/KawasakiWM89
Shumpei Kawasaki, Mitsuru Watabe, Shigeki Morinaga:
A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming. IEEE Micro 9(3): 26-44 (1989)

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