"The architecture of the Sure System 2000 communications processor."

Akira Kabemoto, Hiroshi Yoshida (1991)

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DOI: 10.1109/40.85724

access: closed

type: Journal Article

metadata version: 2017-05-20

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  - https://dblp.org/rec/journals/micro/KabemotoY91
Akira Kabemoto, Hiroshi Yoshida:
The architecture of the Sure System 2000 communications processor. IEEE Micro 11(4): 28-31 (1991)

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