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"Low power and low area VLSI implementation of vedic design FIR filter for ..."

M. Sumalatha, P. V. Naganjaneyulu, K. Satya Prasad (2019)

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DOI: 10.1016/J.MICPRO.2019.102883

access: closed

type: Journal Article

metadata version: 2021-10-14

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M. Sumalatha, P. V. Naganjaneyulu, K. Satya Prasad:
Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising. Microprocess. Microsystems 71 (2019)

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