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ORCID"VLSI design of APT-VDF using novel variable block sized ternary adder and ..."
Aditya Mandloi, Santosh Pawar (2020)
- Aditya Mandloi, Santosh Pawar
:
VLSI design of APT-VDF using novel variable block sized ternary adder and multiplier. Microprocess. Microsystems 78: 103266 (2020)
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