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ORCID"A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 ..."
Hangi Park et al. (2022)
- Hangi Park
, Chanwoong Hwang, Taeho Seong, Jaehyouk Choi:
A Low-Jitter Ring-DCO-Based Fractional-N Digital PLL With a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. IEEE J. Solid State Circuits 57(12): 3527-3537 (2022)
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