Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a ..."

Hideyuki Nosaka et al. (2004)

> Home

Details and statistics

DOI: 10.1109/JSSC.2004.831463

access: closed

type: Journal Article

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/NosakaSIIKYSFYE04
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/NosakaSIIKYSFYE04
Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi:
A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. IEEE J. Solid State Circuits 39(8): 1361-1365 (2004)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.