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"Dynamically shift-switched dataline redundancy suitable for DRAM macro ..."
Toshimasa Namekawa et al. (2000)
- Toshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata:
Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus. IEEE J. Solid State Circuits 35(5): 705-712 (2000)
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