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"A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM."

Hiroalu Nambu et al. (1995)

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DOI: 10.1109/4.375971

access: closed

type: Journal Article

metadata version: 2023-05-05

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  dblp key:
  - journals/jssc/NambuKIMHaUYKIOKH95
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  persistent URL:
  - https://dblp.org/rec/journals/jssc/NambuKIMHaUYKIOKH95
Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma:
A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM. IEEE J. Solid State Circuits 30(4): 491-499 (1995)

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