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"A BiCMOS dynamic multiplier using Wallace tree reduction architecture and ..."

James B. Kuo, K. W. Su, J. H. Lou (1995)

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DOI: 10.1109/4.400440

access: closed

type: Journal Article

metadata version: 2023-05-03

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James B. Kuo, K. W. Su, J. H. Lou:
A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuit. IEEE J. Solid State Circuits 30(8): 950-954 (1995)

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