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"High-speed, low-power, bipolar standard cell design methodology for Gbit/s ..."

Keiichi Koike et al. (1998)

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DOI: 10.1109/4.720400

access: closed

type: Journal Article

metadata version: 2022-07-05

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Keiichi Koike, Kenji Kawai, Akira Onozawa, Yuichiro Takei, Yoshiji Kobayashi, Haruhiko Ichino:
High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing. IEEE J. Solid State Circuits 33(10): 1536-1544 (1998)

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