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"Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array ..."

Tohru Kimura et al. (1995)

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DOI: 10.1109/4.387066

access: closed

type: Journal Article

metadata version: 2023-05-03

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Tohru Kimura, Kazuyuki Nakamura, Yoshiharu Aimoto, Takashi Manabe, Nobuyuki Yamashita, Yoshihiro Fujita, Shin'ichiro Okazaki, Masakazu Yamashina:
Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications. IEEE J. Solid State Circuits 30(6): 637-643 (1995)

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