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"A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using ..."

Jun-Hwan Jang et al. (2022)

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DOI: 10.1109/JSSC.2022.3144437

access: closed

type: Journal Article

metadata version: 2022-08-08

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Jun-Hwan Jang, Hui-Dong Gwon, Tae-Hwang Kong, Jun-Hyeok Yang, Byong-Deok Choi:
A 0.5-1 V, -68 dB Power Supply Rejection Capacitorless Analog LDO Using Voltage-to-Time Conversion in 28-nm CMOS. IEEE J. Solid State Circuits 57(8): 2462-2473 (2022)

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