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"Limitations and challenges of multigigabit DRAM chip design."

Kiyoo Itoh et al. (1997)

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DOI: 10.1109/4.568820

access: closed

type: Journal Article

metadata version: 2022-07-07

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  - https://dblp.org/rec/journals/jssc/ItohNKW97
Kiyoo Itoh, Yoshinobu Nakagome, Shin'ichiro Kimura, Takao Watanabe:
Limitations and challenges of multigigabit DRAM chip design. IEEE J. Solid State Circuits 32(5): 624-634 (1997)

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