"A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With ..."

Satoshi Ishikura et al. (2008)

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DOI: 10.1109/JSSC.2008.917568

access: closed

type: Journal Article

metadata version: 2020-08-30

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Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu:
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues. IEEE J. Solid State Circuits 43(4): 938-945 (2008)

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