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"64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency."

Raymond A. Heald et al. (1998)

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DOI: 10.1109/4.726558

access: closed

type: Journal Article

metadata version: 2022-07-05

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  - journals/jssc/HealdSRKKLLP98
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  - https://dblp.org/rec/journals/jssc/HealdSRKKLLP98
Raymond A. Heald, Ken Shin, Vinita Reddy, I-Feng Kao, Masood Khan, William L. Lynch, Gary Lauterbach, Joe Petolino:
64-KByte sum-addressed-memory cache with 1.6-ns cycle and 2.6-ns latency. IEEE J. Solid State Circuits 33(11): 1682-1689 (1998)

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