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"A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly ..."

Seyed Danesh et al. (2013)

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DOI: 10.1109/JSSC.2013.2237672

access: closed

type: Journal Article

metadata version: 2020-08-30

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Seyed Danesh, Jed Hurwitz, Keith Findlater, David R. Renshaw, Robert K. Henderson:
A Reconfigurable 1 GSps to 250 MSps, 7-bit to 9-bit Highly Time-Interleaved Counter ADC with Low Power Comparator Design. IEEE J. Solid State Circuits 48(3): 733-748 (2013)

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