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"A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell ..."

Azeez J. Bhavnagarwala et al. (2008)

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DOI: 10.1109/JSSC.2008.917506

access: closed

type: Journal Article

metadata version: 2023-09-19

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Azeez J. Bhavnagarwala, Stephen Kosonocky, Carl Radens, Yuen H. Chan, Kevin Stawiasz, Uma Srinivasan, Steven P. Kowalczyk, Matthew M. Ziegler:
A Sub-600-mV, Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing. IEEE J. Solid State Circuits 43(4): 946-955 (2008)

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