"A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET ..."

James Bailey et al. (2022)

> Home

Details and statistics

DOI: 10.1109/JSSC.2021.3109167

access: closed

type: Journal Article

metadata version: 2022-03-23

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/BaileySNMKLCT22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/BaileySNMKLCT22
James Bailey, Hossein Shakiba, Ehud Nir, Grigory Marderfeld, Peter Krotnev, Marc-Andre LaCroix, David Cassan, Davide Tonietto:
A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. IEEE J. Solid State Circuits 57(1): 32-43 (2022)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.